- Manage ASIC/FPGA project lifecycle, from requirements, design, technical architecture, implementation, testing, acceptance, training, and documentation.
- Maintain close monitoring of project progress and report potential risks and challenges in a timely manner with proposed course of actions.
- Determine and manage resources from start to finish with attention to budgetary limitations.
- Build and maintain relationships with external stakeholders.
- Oversee and/or prepare incoming and outgoing project documentation. • Technical leadership of project team.
- Perform HDL coding, synthesis, verification, timing closure, tapeout for project.
Requirements
- A bachelor’s or master’s degree in engineering or relevant fields.
- Strong team leader and individual contributor.
- Experienced candidate with experience in project management or team lead in product development.
- Experienced in HDL coding, FPGA implementation and ASIC tapeout.
If you are interested in the position , kindly send your CVs to sean.ho(@)randstad.com.sg
Please include your availability, expected salary and reason for leaving current job
We regret that only shortlisted candidates will be contacted
Applicants must be fully vaccinated or have a valid exemption in accordance with MOM’s regulations to allow them to enter the workplace. Applicants may be required to share verifiable COVID-19 vaccination documents or proof of a valid exemption at the point of offer. Randstad Pte. Limited and/or the Client reserves the right to withdraw an offer if the applicant fails to provide verifiable COVID-19 vaccination and/or proof of exemption documents. EA: 94C3609 / Reg: R21103172