Roles and Responsibilities
Assume the Technical Leadership role in a Functional Verification team.
Improve existing design verification methodology, tools and flows
Development of UVM Environment, test plan and test benches.
Develop verification plans at module and sub-system level.
Development of Verification Test benches based on
? Coverage driven metrics
? Constrained Random Stimulus generation.
? Assertion based formal checking.
? Property checking / Behavioral model development
Work as one team with other R&D functional teams, define and implement test features required for bring up, debug, validation, characterization, and production.
Assist designers in debug and mentor junior verification engineers
Participate in ASIC and FPGA chip bringup on PCB and in systems
Leverage verification tests for system diagnostic test and production test, where applicable
BS degree with 12 years/MS with 10 years of experience
Strong background in UVM/OVM architecture for verification, functional coverage
Be familiar with Verilog/SystemVerilog, TCL, Perl, C/C++
Be familiar with the simulation tools and flow, e.g. irun, vcs
Demonstrated technical abilities and capable of leading and solving technical challenges. Ability to work cross-functionally.
Energetic. Self-driven. Good communication, organization, analytical, people, project planning, and leadership skills.